Increases in sizes of electronic system circuit designs have accompanied advances in circuit integration. One way in which electronic design automation tools have attempted to meet the challenges of large designs is with hierarchical design flows. In a hierarchical design flow the design is partitioned into portions that are easier to manage. The portions may be separately compiled, simulated, and debugged, and then subsequently combined into a complete system.
The process of combining a number of portions of a design into the complete design may be error prone. Errors may be introduced through inadvertently giving different objects the same name. Since connectivity between elements in a netlist is implied by the names of the elements, assigning the same name to an object in one portion of the design and to another object in a separately compiled portion of the design would likely produce undesirable results when the portions are combined.